Multi-Net Optimization of VLSI Interconn

Spar {0}
Spar {0} som ARK-VENN
{0} til nettpris
med Klikk&Hent
Format/språk
   Klikk og hent - få varen innen 1 time*
   90 dagers åpent kjøp.
* Gjelder varer på lager i butikk

Kort om boken

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, …

Oppdag mer

Velg tagger...

    Om Multi-Net Optimization of VLSI Interconn

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.

    Kundevurderinger

    Totalvurdering: 

    Gi din vurdering: 
    Totalvurdering: 

    Detaljer

    Format
    E-Bok
    Kopisperre
    Teknisk DRM
    Filformat
    PDF
    Utgivelsesår
    2014
    Forlag
    Springer New York
    Språk
    Engelsk
    ISBN
    9781461408215

    Anbefalt

    Nettleseren din er utdatert

    Mye funksjonalitet på ark.no støttes ikke lenger i Internet Explorer. Vennligst bruk en nyere nettleser.