Minimizing and Exploiting Leakage in VLS

Minimizing and Exploiting Leakage in VLS

Nettpris
1 574,-
Førpris 2 249,- Spar 675,-
E-Bok
E-bøkene legges i din ARK-leseapp. Bøkene kan også lastes ned fra Din side.
×
Logg deg inn for å gjennomføre dette kjøpet med ett klikk!

Etter at kjøpet er gjennomført vil boken være tilgjengelig på «din side» og i ARK-appen
Skriv anmeldelse
Format E-Bok
Kopisperre Teknisk DRM
Filformat PDF
Utgivelsesår 2009
Forlag Springer US
Språk Engelsk
ISBN 9781441909503
Se flere detaljer  

Om Minimizing and Exploiting Leakage in VLS

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub- threshold logic.


Kundevurderinger

ARKs anbefalinger

Det finnes ingen vurderinger av dette produktet. Skriv anmeldelse

Mer fra Nikhil Jayakumar; Rajesh Garg; Suganth Paul

Anbefalt


Tips en venn