Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the vast numbers of gates now available. This work outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. It is an attempt to capture and improve on current practices in the industry, and to give a coherent, integrated view of the design process.